1. Field of the Invention
The present invention relates generally to phase-lock loop (PLL) clock generation circuits, and more specifically, to a numerically-controlled PLL for providing a clock signal synchronized to an input timing reference signal.
2. Background of the Invention
Digital audio systems are prevalent in the areas of home entertainment, professional production of multimedia and computer reproduction and generation of multimedia sources. Increasingly, digital audio data is transported from sub-system to sub-system and device to device in both consumer and professional installations, and the data is generally provided with, or has embedded, a timing reference that has too much jitter to act as a stable sample clock reference. Furthermore, the timing information may be provided at a frequency that is lower than the clock rate needed to operate a digital audio sink, such as a digital-to-analog converter (DAC) that receives the incoming digital audio data stream.
Therefore, clock generation circuits that provide stable clock references synchronized to a digital audio stream's timing information are frequently required. The clock generating circuits must generally provide a low-jitter clock from a timing reference that may have a large amount of jitter present and/or from an additional interface clock that also may have a large amount of jitter. Further, such circuits in A/V applications must handle a wide range of potential input frequencies. The clock generation is typically provided by a phase-lock loop (PLL) and the loop bandwidth of the PLL is dictated in part by the frequency range over which the PLL must acquire (capture) and lock in a stable manner. However, wider-bandwidth PLLs have higher noise figures. Further, an input signal is not always available, or may be of degraded or varying quality such that operation of the PLL in synchronization with a clock input signal is not practical or possible.
Therefore, it would be desirable to provide a PLL synchronization circuit and method that provides for narrower bandwidth operation, while able to lock to a wide range of input signal frequencies. It would further be desirable to provide such a PLL that can operate without an input clock signal of sufficient quality for synchronized PLL operation.